From eb74df729e33a68a6ab2b1994602066e9106d405 Mon Sep 17 00:00:00 2001 From: Ted Pavlic Date: Mon, 23 Feb 2009 10:14:16 -0500 Subject: [PATCH] Change two Makefile.common var references to use $() over ${}. Both are legal in Makefiles, but $() matches local convention, and $() prevents confusion about when the variable is expanded (i.e., shell vs. make). --- common/Makefile.common | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/Makefile.common b/common/Makefile.common index 0ae474c3..c1458a87 100644 --- a/common/Makefile.common +++ b/common/Makefile.common @@ -81,11 +81,11 @@ $(RDF): $(RDF_IN) Makefile < $< > $@ @echo "SUCCESS: $@" -clean: ${LOCALEDIR}/$(LOCALES:%=%.clean) +clean: $(LOCALEDIR)/$(LOCALES:%=%.clean) @echo "General $(NAME) cleanup..." rm -f $(JAR) $(XPI) -distclean: ${LOCALEDIR}/$(LOCALES:%=%.distclean) clean +distclean: $(LOCALEDIR)/$(LOCALES:%=%.distclean) clean @echo "More $(NAME) cleanup..." rm -rf $(BUILD_DIR)