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Add tests to repository
This commit is contained in:
Jan Larres
306
tests/vhdl/gcd2.vhd
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306
tests/vhdl/gcd2.vhd
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@@ -0,0 +1,306 @@
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----------------------------------------------------------------------
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-- GCD CALCULATOR (ESD book figure 2.11)
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-- Weijun Zhang, 04/2001
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--
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-- we can put all the components in one document(gcd2.vhd)
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-- or put them in separate files
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-- this is the example of RT level modeling (FSM + DataPath)
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-- the code is synthesized by Synopsys design compiler
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----------------------------------------------------------------------
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-- Component: MULTIPLEXOR --------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity mux is
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port( rst, sLine: in std_logic;
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load, result: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end mux;
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architecture mux_arc of mux is
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begin
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process( rst, sLine, load, result )
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begin
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if( rst = '1' ) then
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output <= "0000"; -- do nothing
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elsif sLine = '0' then
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output <= load; -- load inputs
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else
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output <= result; -- load results
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end if;
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end process;
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end mux_arc;
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-- Component: COMPARATOR ---------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity comparator is
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port( rst: in std_logic;
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x, y: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 1 downto 0 )
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);
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end comparator;
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architecture comparator_arc of comparator is
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begin
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process( x, y, rst )
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begin
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if( rst = '1' ) then
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output <= "00"; -- do nothing
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elsif( x > y ) then
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output <= "10"; -- if x greater
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elsif( x < y ) then
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output <= "01"; -- if y greater
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else
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output <= "11"; -- if equivalance.
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end if;
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end process;
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end comparator_arc;
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-- Component: SUBTRACTOR ----------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity subtractor is
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port( rst: in std_logic;
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cmd: in std_logic_vector( 1 downto 0 );
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x, y: in std_logic_vector( 3 downto 0 );
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xout, yout: out std_logic_vector( 3 downto 0 )
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);
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end subtractor;
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architecture subtractor_arc of subtractor is
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begin
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process( rst, cmd, x, y )
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begin
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if( rst = '1' or cmd = "00" ) then -- not active.
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xout <= "0000";
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yout <= "0000";
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elsif( cmd = "10" ) then -- x is greater
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xout <= ( x - y );
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yout <= y;
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elsif( cmd = "01" ) then -- y is greater
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xout <= x;
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yout <= ( y - x );
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else
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xout <= x; -- x and y are equal
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yout <= y;
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end if;
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end process;
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end subtractor_arc;
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-- Component: REGISTER ---------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity regis is
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port( rst, clk, load: in std_logic;
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input: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end regis;
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architecture regis_arc of regis is
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begin
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process( rst, clk, load, input )
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begin
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if( rst = '1' ) then
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output <= "0000";
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elsif( clk'event and clk = '1') then
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if( load = '1' ) then
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output <= input;
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end if;
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end if;
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end process;
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end regis_arc;
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-- component: FSM controller --------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity fsm is
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port( rst, clk, proceed: in std_logic;
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comparison: in std_logic_vector( 1 downto 0 );
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enable, xsel, ysel, xld, yld: out std_logic
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);
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end fsm;
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architecture fsm_arc of fsm is
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type states is ( init, s0, s1, s2, s3, s4, s5 );
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signal nState, cState: states;
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begin
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process( rst, clk )
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begin
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if( rst = '1' ) then
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cState <= init;
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elsif( clk'event and clk = '1' ) then
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cState <= nState;
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end if;
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end process;
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process( proceed, comparison, cState )
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begin
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case cState is
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when init => if( proceed = '0' ) then
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nState <= init;
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else
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nState <= s0;
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end if;
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when s0 => enable <= '0';
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xsel <= '0';
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ysel <= '0';
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xld <= '0';
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yld <= '0';
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nState <= s1;
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when s1 => enable <= '0';
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xsel <= '0';
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ysel <= '0';
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xld <= '1';
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yld <= '1';
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nState <= s2;
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when s2 => xld <= '0';
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yld <= '0';
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if( comparison = "10" ) then
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nState <= s3;
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elsif( comparison = "01" ) then
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nState <= s4;
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elsif( comparison = "11" ) then
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nState <= s5;
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end if;
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when s3 => enable <= '0';
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xsel <= '1';
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ysel <= '0';
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xld <= '1';
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yld <= '0';
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nState <= s2;
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when s4 => enable <= '0';
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xsel <= '0';
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ysel <= '1';
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xld <= '0';
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yld <= '1';
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nState <= s2;
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when s5 => enable <= '1';
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xsel <= '1';
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ysel <= '1';
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xld <= '1';
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yld <= '1';
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nState <= s0;
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when others => nState <= s0;
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end case;
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end process;
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end fsm_arc;
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----------------------------------------------------------------------
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-- GCD Calculator: top level design using structural modeling
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-- FSM + Datapath (mux, registers, subtracter and comparator)
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----------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use work.all;
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entity gcd is
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port( rst, clk, go_i: in std_logic;
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x_i, y_i: in std_logic_vector( 3 downto 0 );
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d_o: out std_logic_vector( 3 downto 0 )
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);
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end gcd;
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architecture gcd_arc of gcd is
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component fsm is
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port( rst, clk, proceed: in std_logic;
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comparison: in std_logic_vector( 1 downto 0 );
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enable, xsel, ysel, xld, yld: out std_logic
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);
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end component;
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component mux is
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port( rst, sLine: in std_logic;
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load, result: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end component;
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component comparator is
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port( rst: in std_logic;
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x, y: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 1 downto 0 )
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);
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end component;
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component subtractor is
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port( rst: in std_logic;
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cmd: in std_logic_vector( 1 downto 0 );
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x, y: in std_logic_vector( 3 downto 0 );
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xout, yout: out std_logic_vector( 3 downto 0 )
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);
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end component;
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component regis is
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port( rst, clk, load: in std_logic;
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input: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end component;
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signal xld, yld, xsel, ysel, enable: std_logic;
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signal comparison: std_logic_vector( 1 downto 0 );
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signal result: std_logic_vector( 3 downto 0 );
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signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );
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begin
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-- doing structure modeling here
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-- FSM controller
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TOFSM: fsm port map( rst, clk, go_i, comparison,
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enable, xsel, ysel, xld, yld );
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-- Datapath
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X_MUX: mux port map( rst, xsel, x_i, xsub, xmux );
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Y_MUX: mux port map( rst, ysel, y_i, ysub, ymux );
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X_REG: regis port map( rst, clk, xld, xmux, xreg );
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Y_REG: regis port map( rst, clk, yld, ymux, yreg );
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U_COMP: comparator port map( rst, xreg, yreg, comparison );
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X_SUB: subtractor port map( rst, comparison, xreg, yreg, xsub, ysub );
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OUT_REG: regis port map( rst, clk, enable, xsub, result );
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d_o <= result;
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end gcd_arc;
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---------------------------------------------------------------------------
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91
tests/vhdl/test_multpipe.vhdl
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91
tests/vhdl/test_multpipe.vhdl
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@@ -0,0 +1,91 @@
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--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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--* * * * * * * * * * * * * * * * VHDL Source Code * * * * * * * * * * * * * *
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--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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--* Title : Test_MultPipe
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--* Filename & Ext : test_multpipe.vhdl
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--* Author : David Bishop <dbishop@vhdl.org> X-XXXXX
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--* Created : 1999/03/12
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--* Last modified : $Date: 1999-03-12 16:41:40-05 $
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--* WORK Library : testchip_lib
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--* Description : A pipline multiplier with lots of redundant logic
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--* Known Bugs :
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--* :
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--* RCS Summary : $Id: test_multpipe.vhdl,v 1.1 1999-03-12 16:41:40-05 bishop Exp bishop $
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--* :
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--* Mod History : $Log: test_multpipe.vhdl,v $
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--* Mod History : Revision 1.1 1999-03-12 16:41:40-05 bishop
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--* Mod History : Initial revision
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--* Mod History :
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--* :
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--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity test_multpipe is
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generic ( width : integer := 7 );
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port ( clk : in std_ulogic;
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reset : in std_ulogic;
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enable : in std_ulogic;
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inp1, inp2 : in std_logic_vector ( width downto 0);
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sum : out std_logic_vector ( (width * 2 ) downto 0) );
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end test_multpipe;
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architecture rtl of test_multpipe is
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subtype vectors is std_logic_vector (( width * 2 ) downto 0 );
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subtype unsigneds is unsigned (( width * 2 ) downto 0 );
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type stage_array is array ( width downto 0 ) of vectors;
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type adder_array is array ( width downto 0 ) of unsigneds;
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signal stage1, stage2 : stage_array;
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signal adder_stage : adder_array;
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signal reg_stage : adder_array;
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begin -- rtl
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-- Fill the two arrays
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build_stage1 : process ( inp1 )
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begin
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stage_loop1 : for i in 0 to width loop
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stage1 ( i ) <= ( others => '0' );
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stage1 ( i ) ( width + i downto i ) <= inp1;
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end loop stage_loop1;
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end process build_stage1;
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build_stage2 : process ( inp2 )
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begin
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stage_loop2 : for i in 0 to width loop
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stage2 ( i ) <= ( others => inp2 ( i ) );
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end loop stage_loop2;
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end process build_stage2;
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-- and the two arrays together, now you have a matrix which
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-- you can add up.
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and_stages : process ( stage1, stage2 )
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begin
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and_loop : for i in 0 to width loop
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adder_stage ( i ) <= unsigned ( stage1 ( i ) and stage2 ( i ) );
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end loop and_loop;
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end process and_stages;
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register_stages : process ( reset, clk )
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variable local_sum : unsigned ( sum'high downto 0 );
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||||
begin
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if reset = '0' then
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reset_loop : for i in 0 to width loop
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reg_stage ( i ) <= ( others => '0' );
|
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end loop reset_loop;
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elsif rising_edge ( clk ) then
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if enable = '1' then
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adder_loop : for i in 0 to ( width + 1 ) / 2 loop
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reg_stage ( i ) <= adder_stage ( i ) + adder_stage ( width - i );
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end loop adder_loop;
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reg_stage ( 4 ) <= reg_stage ( 0 ) + reg_stage ( 3 );
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reg_stage ( 5 ) <= reg_stage ( 1 ) + reg_stage ( 2 );
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reg_stage ( 6 ) <= reg_stage ( 4 ) + reg_stage ( 5 );
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||||
end if;
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||||
end if;
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||||
end process register_stages;
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sum <= std_logic_vector (reg_stage ( 6 ));
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end rtl;
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67
tests/vhdl/test_parity.vhdl
Normal file
67
tests/vhdl/test_parity.vhdl
Normal file
@@ -0,0 +1,67 @@
|
||||
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
--* * * * * * * * * * * * * * * * VHDL Source Code * * * * * * * * * * * * * *
|
||||
--* * * Copyright (C) 1997 - Eastman Kodak Company - All Rights Reserved * * *
|
||||
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
--* Title : TEST_PARITY
|
||||
--* Filename & Ext : test_parity.vhdl
|
||||
--* Author : David Bishop X-66788
|
||||
--* Created : 3/18/97
|
||||
--* Version : 1.2
|
||||
--* Revision Date : 97/04/15
|
||||
--* SCCSid : 1.2 04/15/97 test_parity.vhdl
|
||||
--* WORK Library : testchip
|
||||
--* Mod History :
|
||||
--* Description : This is a parity generator which is written recursively
|
||||
--* : It is designed to test the ability of Simulation and
|
||||
--* : Synthesis tools to check this capability.
|
||||
--* Known Bugs :
|
||||
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
|
||||
-- Parity is done in a recursively called function.
|
||||
-- Package definition
|
||||
package Parity_Pack is
|
||||
function Recursive_Parity ( BUSX : std_logic_vector )
|
||||
return std_ulogic;
|
||||
end Parity_Pack;
|
||||
|
||||
-- Package body.
|
||||
package body Parity_Pack is
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||||
function Recursive_Parity ( BUSX : std_logic_vector )
|
||||
return std_ulogic is
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||||
variable Upper, Lower : std_ulogic;
|
||||
variable Half : integer;
|
||||
variable BUS_int : std_logic_vector ( BUSX'length - 1 downto 0 );
|
||||
variable Result : std_logic;
|
||||
begin
|
||||
BUS_int := BUSX;
|
||||
if ( BUS_int'length = 1 ) then
|
||||
Result := BUS_int ( BUS_int'left );
|
||||
elsif ( BUS_int'length = 2 ) then
|
||||
Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left );
|
||||
else
|
||||
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
|
||||
Upper := Recursive_Parity ( BUS_int ( BUS_int'left downto Half ));
|
||||
Lower := Recursive_Parity ( BUS_int ( Half - 1 downto BUS_int'right ));
|
||||
Result := Upper xor Lower;
|
||||
end if;
|
||||
return Result;
|
||||
end;
|
||||
end Parity_Pack;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use work.Parity_Pack.all;
|
||||
|
||||
entity Test_Parity is
|
||||
generic ( WIDTH : integer := 16);
|
||||
port ( BUSX : in std_logic_vector ( WIDTH downto 0 );
|
||||
Parity : out std_ulogic );
|
||||
end Test_Parity;
|
||||
|
||||
architecture RTL of Test_Parity is
|
||||
begin
|
||||
Parity <= Recursive_Parity ( BUSX );
|
||||
end RTL;
|
||||
219
tests/vhdl/testchip_core.vhdl
Normal file
219
tests/vhdl/testchip_core.vhdl
Normal file
@@ -0,0 +1,219 @@
|
||||
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
--* * * * * * * * * * * * * * * * VHDL Source Code * * * * * * * * * * * * * *
|
||||
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
--* Title : TESTCHIP_CORE
|
||||
--* Filename & Ext : testchip_core.vhdl
|
||||
--* Author : David W. Bishop
|
||||
--* Created : 6/6/96
|
||||
--* Version : 1.1
|
||||
--* Revision Date : 97/12/03
|
||||
--* SCCSid : 1.1 12/03/97 testchip_core.vhdl
|
||||
--* WORK Library : chiptest
|
||||
--* Mod History :
|
||||
--* Description : This is a test chip core, designed to test several
|
||||
--* : functions in Synthesis and simulation
|
||||
--* Known Bugs :
|
||||
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity testchip_core is
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
dclk : in std_ulogic;
|
||||
dclk_i : out std_ulogic;
|
||||
slow_count : out std_logic_vector ( 4 downto 0 );
|
||||
enable : in std_ulogic;
|
||||
load : in std_ulogic;
|
||||
input_data : in std_logic_vector ( 7 downto 0 );
|
||||
shout : out std_ulogic;
|
||||
control : out std_logic_vector ( 1 downto 0 );
|
||||
count : out std_logic_vector ( 7 downto 0 );
|
||||
sum : out std_logic_vector ( 8 downto 0 );
|
||||
mulout : out std_logic_vector ( 14 downto 0 );
|
||||
parity : out std_ulogic );
|
||||
end testchip_core;
|
||||
|
||||
architecture rtl of testchip_core is
|
||||
|
||||
--------------------------------------------------------------------------------- Start with the declarations for the sub-blocks
|
||||
-------------------------------------------------------------------------------
|
||||
component Test_ClkGen
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
dclk : out std_ulogic );
|
||||
end component;
|
||||
|
||||
component test_counter
|
||||
generic ( width : integer := 17 );
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
enable : in std_ulogic;
|
||||
count : out std_logic_vector ( width - 1 downto 0) );
|
||||
end component;
|
||||
|
||||
component test_add
|
||||
generic ( width : integer := 17 );
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
enable : in std_ulogic;
|
||||
inp1 : in std_logic_vector ( width downto 0);
|
||||
inp2 : in std_logic_vector ( width downto 0);
|
||||
sum : out std_logic_vector ( (width + 1) downto 0) );
|
||||
end component;
|
||||
|
||||
component test_reg
|
||||
generic ( width : integer := 17 );
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
enable : in std_ulogic;
|
||||
sel : in std_ulogic;
|
||||
inp1 : in std_logic_vector ( width downto 0);
|
||||
inp2 : in std_logic_vector ( width downto 0);
|
||||
outpt : out std_logic_vector ( width downto 0) );
|
||||
end component;
|
||||
|
||||
component test_shift
|
||||
generic ( width : integer := 17 );
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
load : in std_ulogic;
|
||||
en : in std_ulogic;
|
||||
inp : in std_logic_vector ( width downto 0 );
|
||||
outp : out std_ulogic );
|
||||
end component;
|
||||
|
||||
component test_state
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
con1, con2, con3 : in std_ulogic;
|
||||
out1, out2 : out std_ulogic );
|
||||
end component;
|
||||
|
||||
component test_multpipe
|
||||
generic ( width : integer := 7 );
|
||||
port ( clk : in std_ulogic;
|
||||
reset : in std_ulogic;
|
||||
enable : in std_ulogic;
|
||||
inp1, inp2 : in std_logic_vector ( width downto 0);
|
||||
sum : out std_logic_vector ( (width * 2 ) downto 0) );
|
||||
end component;
|
||||
|
||||
component test_parity
|
||||
generic ( WIDTH : integer := 16);
|
||||
port ( BUSX : in std_logic_vector ( WIDTH downto 0 );
|
||||
Parity : out std_ulogic );
|
||||
end component;
|
||||
|
||||
-- Signal declarations
|
||||
signal internal_data : std_logic_vector ( input_data'high downto 0 );
|
||||
signal local_count : std_logic_vector ( input_data'high downto 0 );
|
||||
signal local_mulout : std_logic_vector ( mulout'high downto 0 );
|
||||
signal VCC, GND : std_ulogic;
|
||||
|
||||
begin -- rtl
|
||||
|
||||
VCC <= '1';
|
||||
GND <= '0';
|
||||
mulout <= local_mulout;
|
||||
|
||||
U1 : test_clkgen
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
dclk => dclk_i );
|
||||
|
||||
U2 : test_counter
|
||||
generic map ( width => 5 )
|
||||
port map (
|
||||
clk => dclk,
|
||||
reset => reset,
|
||||
enable => VCC,
|
||||
count => slow_count
|
||||
);
|
||||
|
||||
U3 : test_reg
|
||||
generic map ( width => internal_data'high )
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
enable => VCC,
|
||||
sel => VCC,
|
||||
inp1 => input_data,
|
||||
inp2 => local_count,
|
||||
outpt => internal_data
|
||||
);
|
||||
|
||||
U4 : test_counter
|
||||
generic map ( width => internal_data'high + 1 )
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
enable => enable,
|
||||
count => local_count
|
||||
);
|
||||
|
||||
U7 : test_add
|
||||
generic map ( width => internal_data'high )
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
enable => enable,
|
||||
inp1 => local_count,
|
||||
inp2 => internal_data,
|
||||
sum => sum
|
||||
);
|
||||
|
||||
U5 : test_shift
|
||||
generic map ( width => internal_data'high )
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
en => enable,
|
||||
load => load,
|
||||
inp => internal_data,
|
||||
outp => shout
|
||||
);
|
||||
|
||||
U9 : test_state
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
con1 => local_count ( 0 ),
|
||||
con2 => local_count ( 1 ),
|
||||
con3 => local_count ( 2 ),
|
||||
out1 => control ( 0 ),
|
||||
out2 => control ( 1 )
|
||||
);
|
||||
|
||||
U8 : test_multpipe
|
||||
generic map ( width => internal_data'high )
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
enable => enable,
|
||||
inp1 => local_count,
|
||||
inp2 => internal_data,
|
||||
sum => local_mulout );
|
||||
|
||||
U6 : Test_Parity
|
||||
generic map ( Width => internal_data'high )
|
||||
port map (
|
||||
BUSX => internal_data,
|
||||
Parity => parity );
|
||||
|
||||
U10 : test_reg
|
||||
generic map ( width => count'high )
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
enable => VCC,
|
||||
sel => GND,
|
||||
inp1 => input_data,
|
||||
inp2 => local_count,
|
||||
outpt => count
|
||||
);
|
||||
|
||||
|
||||
end rtl;
|
||||
Reference in New Issue
Block a user