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Add tests to repository
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Jan Larres
306
tests/vhdl/gcd2.vhd
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306
tests/vhdl/gcd2.vhd
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----------------------------------------------------------------------
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-- GCD CALCULATOR (ESD book figure 2.11)
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-- Weijun Zhang, 04/2001
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--
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-- we can put all the components in one document(gcd2.vhd)
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-- or put them in separate files
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-- this is the example of RT level modeling (FSM + DataPath)
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-- the code is synthesized by Synopsys design compiler
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----------------------------------------------------------------------
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-- Component: MULTIPLEXOR --------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity mux is
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port( rst, sLine: in std_logic;
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load, result: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end mux;
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architecture mux_arc of mux is
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begin
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process( rst, sLine, load, result )
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begin
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if( rst = '1' ) then
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output <= "0000"; -- do nothing
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elsif sLine = '0' then
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output <= load; -- load inputs
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else
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output <= result; -- load results
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end if;
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end process;
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end mux_arc;
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-- Component: COMPARATOR ---------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity comparator is
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port( rst: in std_logic;
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x, y: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 1 downto 0 )
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);
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end comparator;
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architecture comparator_arc of comparator is
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begin
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process( x, y, rst )
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begin
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if( rst = '1' ) then
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output <= "00"; -- do nothing
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elsif( x > y ) then
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output <= "10"; -- if x greater
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elsif( x < y ) then
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output <= "01"; -- if y greater
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else
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output <= "11"; -- if equivalance.
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end if;
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end process;
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end comparator_arc;
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-- Component: SUBTRACTOR ----------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity subtractor is
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port( rst: in std_logic;
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cmd: in std_logic_vector( 1 downto 0 );
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x, y: in std_logic_vector( 3 downto 0 );
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xout, yout: out std_logic_vector( 3 downto 0 )
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);
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end subtractor;
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architecture subtractor_arc of subtractor is
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begin
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process( rst, cmd, x, y )
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begin
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if( rst = '1' or cmd = "00" ) then -- not active.
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xout <= "0000";
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yout <= "0000";
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elsif( cmd = "10" ) then -- x is greater
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xout <= ( x - y );
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yout <= y;
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elsif( cmd = "01" ) then -- y is greater
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xout <= x;
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yout <= ( y - x );
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else
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xout <= x; -- x and y are equal
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yout <= y;
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end if;
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end process;
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end subtractor_arc;
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-- Component: REGISTER ---------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity regis is
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port( rst, clk, load: in std_logic;
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input: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end regis;
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architecture regis_arc of regis is
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begin
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process( rst, clk, load, input )
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begin
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if( rst = '1' ) then
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output <= "0000";
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elsif( clk'event and clk = '1') then
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if( load = '1' ) then
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output <= input;
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end if;
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end if;
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end process;
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end regis_arc;
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-- component: FSM controller --------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity fsm is
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port( rst, clk, proceed: in std_logic;
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comparison: in std_logic_vector( 1 downto 0 );
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enable, xsel, ysel, xld, yld: out std_logic
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);
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end fsm;
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architecture fsm_arc of fsm is
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type states is ( init, s0, s1, s2, s3, s4, s5 );
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signal nState, cState: states;
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begin
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process( rst, clk )
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begin
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if( rst = '1' ) then
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cState <= init;
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elsif( clk'event and clk = '1' ) then
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cState <= nState;
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end if;
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end process;
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process( proceed, comparison, cState )
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begin
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case cState is
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when init => if( proceed = '0' ) then
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nState <= init;
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else
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nState <= s0;
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end if;
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when s0 => enable <= '0';
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xsel <= '0';
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ysel <= '0';
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xld <= '0';
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yld <= '0';
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nState <= s1;
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when s1 => enable <= '0';
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xsel <= '0';
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ysel <= '0';
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xld <= '1';
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yld <= '1';
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nState <= s2;
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when s2 => xld <= '0';
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yld <= '0';
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if( comparison = "10" ) then
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nState <= s3;
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elsif( comparison = "01" ) then
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nState <= s4;
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elsif( comparison = "11" ) then
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nState <= s5;
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end if;
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when s3 => enable <= '0';
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xsel <= '1';
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ysel <= '0';
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xld <= '1';
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yld <= '0';
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nState <= s2;
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when s4 => enable <= '0';
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xsel <= '0';
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ysel <= '1';
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xld <= '0';
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yld <= '1';
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nState <= s2;
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when s5 => enable <= '1';
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xsel <= '1';
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ysel <= '1';
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xld <= '1';
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yld <= '1';
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nState <= s0;
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when others => nState <= s0;
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end case;
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end process;
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end fsm_arc;
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----------------------------------------------------------------------
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-- GCD Calculator: top level design using structural modeling
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-- FSM + Datapath (mux, registers, subtracter and comparator)
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----------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use work.all;
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entity gcd is
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port( rst, clk, go_i: in std_logic;
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x_i, y_i: in std_logic_vector( 3 downto 0 );
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d_o: out std_logic_vector( 3 downto 0 )
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);
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end gcd;
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architecture gcd_arc of gcd is
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component fsm is
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port( rst, clk, proceed: in std_logic;
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comparison: in std_logic_vector( 1 downto 0 );
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enable, xsel, ysel, xld, yld: out std_logic
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);
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end component;
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component mux is
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port( rst, sLine: in std_logic;
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load, result: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end component;
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component comparator is
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port( rst: in std_logic;
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x, y: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 1 downto 0 )
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);
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end component;
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component subtractor is
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port( rst: in std_logic;
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cmd: in std_logic_vector( 1 downto 0 );
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x, y: in std_logic_vector( 3 downto 0 );
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xout, yout: out std_logic_vector( 3 downto 0 )
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);
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end component;
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component regis is
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port( rst, clk, load: in std_logic;
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input: in std_logic_vector( 3 downto 0 );
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output: out std_logic_vector( 3 downto 0 )
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);
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end component;
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signal xld, yld, xsel, ysel, enable: std_logic;
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signal comparison: std_logic_vector( 1 downto 0 );
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signal result: std_logic_vector( 3 downto 0 );
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signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );
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begin
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-- doing structure modeling here
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-- FSM controller
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TOFSM: fsm port map( rst, clk, go_i, comparison,
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enable, xsel, ysel, xld, yld );
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-- Datapath
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X_MUX: mux port map( rst, xsel, x_i, xsub, xmux );
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Y_MUX: mux port map( rst, ysel, y_i, ysub, ymux );
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X_REG: regis port map( rst, clk, xld, xmux, xreg );
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Y_REG: regis port map( rst, clk, yld, ymux, yreg );
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U_COMP: comparator port map( rst, xreg, yreg, comparison );
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X_SUB: subtractor port map( rst, comparison, xreg, yreg, xsub, ysub );
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OUT_REG: regis port map( rst, clk, enable, xsub, result );
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d_o <= result;
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end gcd_arc;
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---------------------------------------------------------------------------
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