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Change two Makefile.common var references to use $() over ${}.

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Both are legal in Makefiles, but $() matches local convention, and $()
prevents confusion about when the variable is expanded (i.e., shell vs.
make).
This commit is contained in:
Ted Pavlic
2009-02-23 10:14:16 -05:00
parent 530670f1a0
commit eb74df729e
1 changed files with 2 additions and 2 deletions
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4
common/Makefile.common
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@@ -81,11 +81,11 @@ $(RDF): $(RDF_IN) Makefile
< $< > $@
@echo "SUCCESS: $@"
clean: ${LOCALEDIR}/$(LOCALES:%=%.clean)
clean: $(LOCALEDIR)/$(LOCALES:%=%.clean)
@echo "General $(NAME) cleanup..."
rm -f $(JAR) $(XPI)
distclean: ${LOCALEDIR}/$(LOCALES:%=%.distclean) clean
distclean: $(LOCALEDIR)/$(LOCALES:%=%.distclean) clean
@echo "More $(NAME) cleanup..."
rm -rf $(BUILD_DIR)