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82 lines
3.4 KiB
C
82 lines
3.4 KiB
C
/* NVClock 0.8 - Linux overclocker for NVIDIA cards
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*
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* Copyright(C) 2001-2007 Roderick Colenbrander
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*
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* site: http://nvclock.sourceforge.net
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/* PCI stuff */
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#define PCI_VENDOR_ID 0x0 /* 16-bit */
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#define PCI_DEVICE_ID 0x2 /* 16-bit */
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#define PCI_CAPABILITY_LIST 0x34
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#define PCI_CAP_LIST_ID 0x0
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#define PCI_CAP_LIST_NEXT 0x1
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#define PCI_CAP_ID_AGP 0x2 /* AGP */
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#define PCI_AGP_STATUS 0x4
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# define PCI_AGP_STATUS_SBA 0x200 /* Sideband Addressing */
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# define PCI_AGP_STATUS_64BIT 0x20
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# define PCI_AGP_STATUS_FW 0x10 /* Fast Writes */
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# define PCI_AGP_STATUS_RATE_8X_SUPPORT 0x8 /* If set AGP1x/AGP2x need to be interpreted as AGP4x/AGP8x */
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# define PCI_AGP_STATUS_RATE_8X_SHIFT 0x2 /* Needs to be used when 8x support is enabled to translate 1x/ -> 4x/8x*/
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# define PCI_AGP_STATUS_RATE_4X 0x4
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# define PCI_AGP_STATUS_RATE_2X 0x2
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# define PCI_AGP_STATUS_RATE_1X 0x1
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# define PCI_AGP_STATUS_RATE_MASK 0x7 /* AGP4X | AGP2X | AGP1X */
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#define PCI_AGP_COMMAND 0x8
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# define PCI_AGP_COMMAND_SBA 0x200 /* Sideband Addressing */
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# define PCI_AGP_COMMAND_AGP 0x100 /* Tells if AGP is enabled */
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# define PCI_AGP_COMMAND_64BIT 0x20
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# define PCI_AGP_COMMAND_FW 0x10 /* Fast Writes */
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# define PCI_AGP_COMMAND_RATE_4X 0x4
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# define PCI_AGP_COMMAND_RATE_2X 0x2
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# define PCI_AGP_COMMAND_RATE_1X 0x1
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# define PCI_AGP_COMMAND_RATE_MASK 0x7 /* AGP4X | AGP2X | AGP1X */
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#define PCI_CAP_ID_EXP 0x10 /* PCI-Express */
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#define PCIE_LINKCAP 0xc
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#define PCIE_LINKCONTROL 0x10
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#define PCIE_LINKSTATUS 0x12
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# define PCIE_LINK_SPEED_MASK 0x3f0
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# define PCIE_LINK_SPEED_SHIFT 4
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/* PMC */
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#define NV_PMC_BOOT_0 0x0
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# define NV_PMC_BOOT_0_REVISION_MINOR 0xf
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# define NV_PMC_BOOT_0_REVISION_MAJOR 0xf0 /* in general A or B, on pre-NV10 it was different */
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# define NV_PMC_BOOT_0_REVISION_MASK 0xff
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/* NV4X registers
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*
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* 0xc040: used to enble/disable parts of the GPU?
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* bit1:0, enable/disable PLL 0x4000/0x4004; perhaps one bit is enable and the other a PLL layout switch?
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* bit3:2, ??
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* bit5:4, seems similar to bit1:0, perhaps for a VPLL? but in various cases it is equal to bit1:0
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* bit7:6, ??
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* bit9:8, seems similar to bit1:0, perhaps for a VPLL? but in various cases it is equal to bit1:0
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* bit11:10, seems related to 0x4030/0x4034 (??)
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* bit12:13, ??
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* bit15:14, seems related to 0x4020/0x4024; perhaps it is for all MPLL ones? (what about bit11:10 then?)
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* bit17:16, seems related to 0x680508/0x680578 (primary VPLL)
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* bit29:28, seems to be off when dumping bios
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*/
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/* NV5x registers
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*
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* The following register is around again but much more bits are used, so start a new description
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* 0xc040: used to enable/disable parts of the GPU
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* bit21:20, used to enable/disable PLL 0x4008/0x400c (gpu clock)
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*/
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